This invention relates to integrated circuit devices and fabrication methods therefor and more particularly to conductive interconnections for integrated circuit devices and fabrication methods therefor.
Integrated circuits are widely used in consumer and commercial products. As the integration density of integrated circuit devices continues to increase, it may become desirable to increase the integration density of the conductive interconnections that are formed on an integrated circuit substrate. Moreover, it also may be desirable to provide more efficient processes for forming the high-density interconnections.
High-density interconnections are particularly desirable for integrated circuit memory devices such as integrated circuit Dynamic Random Access Memory (DRAM) devices. As is well known to those having skill in the art, an integrated circuit memory device generally includes a cell array region wherein an array of memory cells is provided, and a peripheral region that provides control and other circuits for the cell array region. In DRAM devices, data is stored by storing charge on integrated circuit capacitors. Accordingly, it may be desirable to integrate these capacitors with the high-density conductive interconnections for the integrated circuit memory device.
As also is well known to those having skill in the art, DRAM devices may use silicon dioxide, silicon nitride and/or other insulators as the dielectric film for the memory cell capacitors. It also is known to use a ferroelectric film, comprising for example barium titanate and/or other materials, instead of a conventional dielectric film. When a ferroelectric material is used for the dielectric film, a non-volatile memory device may be produced. Thus, the ferroelectric film allows a remnant polarization to be stored in the ferroelectric material so that the memory cell can repeatedly switch between two stable polarization states by means of voltage pulses, thereby providing a non-volatile memory device.
In ferroelectric memory devices, it is known to use refractory metal such as platinum for the capacitor electrodes. Interconnections may be provided using a single level or double level interconnection process using different materials from those of the electrodes. See, for example, the publication entitled Highly Reliable Ferroelectric Memory Technology with Bismuth Layer Structure Thin Film (Y-1 Family) to Fuji et al., IEDM, Vol. 97, pp. 597-600, 1997, wherein a double level metal process is disclosed.
Notwithstanding these and other advances, it continues to be desirable to provide high-density, multilevel conductive interconnections for integrated circuit devices and efficient methods of fabricating the same. It is particularly desirable to provide high-density interconnections for integrated circuit memory devices such as integrated circuit memory devices that use ferroelectric capacitors, and efficient methods of fabricating the same.
It therefore is an object of the present invention to provide improved methods of forming conductive interconnections for integrated circuit devices, and interconnections so formed.
It is another object of the present invention to provide conductive interconnections for integrated circuit memory devices that can integrate capacitors therein, and methods of forming the same.
It is still another object of the present invention to provide conductive interconnections for integrated circuit memory devices that can integrate ferroelectric capacitors therein, and methods of forming the same.
These and other objects are provided, according to an embodiment of the present invention, by forming a first conductive layer, a capacitor dielectric film and a second conductive layer on a first insulating layer on an integrated circuit substrate. The second conductive layer, the capacitor dielectric film and the first conductive layer are patterned to define a plurality of capacitors, each comprising a portion of the first conductive layer, a portion of the capacitor dielectric film thereon and a portion of the second conductive layer thereon, and to define a plurality of first insulating layer patterns that are free of the capacitor dielectric film and the second conductive layer thereon. A second insulating layer is formed on the first insulating layer, on the plurality of capacitors and on the plurality of first conductive patterns. The second insulating layer includes therein a plurality of first contact holes that selectively expose the plurality of first conductive layer patterns.
A first level interconnection is formed in the plurality of first contact holes and on the second insulating layer to electrically contact the plurality of first conductive patterns. A third insulating layer is formed on the second insulating layer and on the first level interconnection. The third insulating layer includes therein a plurality of second contact holes that selectively expose the first level interconnection and selected ones of the plurality of capacitors. A second level interconnection is formed in the plurality of second contact holes and on the third insulating layer to selectively electrically contact the plurality of capacitors and to selectively electrically contact the first level interconnection. The first conductive layer, the second conductive layer, the first level interconnection and the second level interconnection preferably comprise the same material, and the capacitor dielectric film preferably comprises a ferroelectric film.
Accordingly, a multilevel interconnection may be fabricated of the same material as the ferroelectric capacitor electrodes. Moreover, formation of the ferroelectric capacitor and formation of the interconnections may be implemented in the same process chamber to thereby provide an in-situ process that can be efficient.
In preferred embodiments of methods according to the present invention, a plurality of conductive plugs are formed in a first insulating layer on an integrated circuit substrate. A first conductive layer, a capacitor dielectric film and a second conductive layer are formed on the first insulating layer including on the conductive plugs. The second conductive layer, the capacitor dielectric film and the first conductive layer are patterned to define a plurality of capacitors, each comprising a portion of the first conductive layer, a portion of the capacitor dielectric film thereon and a portion of the second conductive layer thereon, and to define a plurality of first conductive layer patterns that are free of the capacitor dielectric film and the second conductive layer thereon. At least a first of the plurality of capacitors is electrically connected to a conductive plug and at least a second of the plurality of capacitors is not electrically connected to a conductive plug.
A second insulating layer is formed on the first insulating layer, on the plurality of capacitors and on the plurality of first conductive patterns. The second insulating layer includes therein a plurality of first contact holes that selectively expose the plurality of first conductive layer patterns. A first level interconnection is formed in the plurality of first contact holes and on the second insulating layer to electrically contact the plurality of first conductive patterns and to selectively electrically interconnect selected ones of the first conductive patterns to one another on the second insulating layer.
A third insulating layer is formed on the second insulating layer and on the first level interconnection. The third insulating layer includes therein a plurality of second contact holes that selectively expose the first level interconnection and selected ones of the plurality of capacitors. A second level interconnection is formed in the plurality of second contact holes and on the third insulating layer to selectively electrically interconnect the at least one of the first capacitors, to selectively electrically contact the first level interconnection and to selectively electrically interconnect selective ones of the at least a second of the plurality of capacitors to one another and to the first level interconnection. Accordingly, by providing the second capacitors that are not electrically connected to a conductive plug, the top electrode of the capacitors may be used in a multilevel interconnection, and the capacitors also can reduce topography differences in an integrated circuit.
According to another aspect of the invention, conductive interconnections for an integrated circuit memory device are fabricated by forming a plurality of first conductive plugs in a first insulating layer on an integrated circuit substrate and forming a first conductive layer, a capacitor dielectric film and a second conductive layer on the first insulating layer including on the first conductive plugs. The second conductive layer, the capacitor dielectric film and the first conductive layer are patterned to define a plurality of capacitors, each comprising a portion of the first conductive layer, a portion of the capacitor dielectric film thereon and a portion of the second conductive layer thereon, such that at least a first of the plurality of capacitors is electrically connected to a first conductive plug and at least a second of the plurality of capacitors is not electrically connected to a first conductive plug. A second insulating layer is formed on the first insulating layer and on the plurality of capacitors. The second insulating layer includes therein a plurality of contact holes that expose the at least a first and second of the plurality of capacitors. A plurality of second conductive plugs is formed in the plurality of contact holes. Accordingly, by providing the second capacitors that are not electrically connected to a first conductive plug, the top electrode of the capacitors may be used in an interconnection, and the capacitors also can reduce topography differences in an integrated circuit.
When the integrated circuit devices are integrated circuit memory devices that include a cell array region and a peripheral region, the plurality of capacitors preferably is defined in the cell array region and in the peripheral region, each comprising a portion of the first conductive layer, a portion of the capacitor dielectric film thereon and a portion of the second conductive layer thereon. The plurality of first conductive layer patterns preferably is defined in the peripheral region, that are free of the capacitor dielectric film and the second conductive layer thereon. Thus, at least a first of the plurality of capacitors in the cell array region is electrically connected to a conductive plug and at least a second of the plurality of capacitors in the peripheral region is not electrically connected to a conductive plug. The capacitors in the peripheral region may be used as part of the multilevel conductive interconnections and also may be used to reduce topography differences between the cell array region and the peripheral region of an integrated circuit memory device.
Conductive interconnections for integrated circuit devices according to embodiments of the invention comprise a first insulating layer on an integrated circuit substrate, the first insulating layer including therein a plurality of conductive plugs. A plurality of capacitors is provided on the first insulating layer. Each capacitor comprises a first portion of the first conductive layer, a portion of the capacitor dielectric film thereon and a portion of the second conductive layer thereon. At least a first of the plurality of capacitors is electrically connected to a conductive plug and at least a second of the plurality of capacitors is not electrically connected to a conductive plug. A plurality of first conductive layer patterns is provided on the first insulating layer. The first conductive layer patterns comprise a second portion of the first conductive layer that is free of the capacitor dielectric film and the second conductive layer thereon.
A second insulating layer is provided on the first insulating layer, on the plurality of capacitors and on the plurality of first conductive patterns. The second insulating layer includes therein a plurality of first contact holes that selectively expose the plurality of first conductive layer patterns. A first level interconnection is provided in the plurality of first contact holes and on the second insulating layer, that electrically contacts the plurality of first conductive patterns and that selectively electrically interconnects selected ones of the first conductive patterns to one another on the second insulating layer.
A third insulating layer is provided on the second insulating layer and on the first level interconnection. The third insulating layer includes therein a plurality of second contact holes that selectively expose the first level interconnection and selected ones of the plurality of capacitors. A second level interconnection is provided in the plurality of second contact holes and on the third insulating layer, that selectively electrically contacts the at least one of the first capacitors, that selectively electrically contacts the first level interconnection and selectively electrically interconnects selected ones of the at least the second of the plurality of capacitors to one another and to the first level interconnection. A plurality of third contact holes also may be provided in the second insulating layer that underlies selected ones of the second contact holes and that selectively expose the first and second capacitors therein.
The first conductive layer, the second conductive layer, the first level interconnection and the second level interconnection preferably all comprise the same material, and the capacitor dielectric film preferably is a ferroelectric film. When the integrated circuit is an integrated circuit memory device including a cell array region and a peripheral region, the at least a first of the plurality of capacitors preferably is located in the cell array region and the at least a second of the plurality of capacitors preferably is located in the peripheral region. The plurality of first conductive layer patterns preferably is located in the peripheral region.
Accordingly, in the cell array region, ferroelectric capacitors are formed that are electrically connected to the underlying contact plugs. In the peripheral region, lower electrode patterns that are electrically connected to the contact plugs may be formed. Pseudo-ferroelectric capacitors, which are not electrically connected to the underlying contact plugs and are made of the same components as the ferroelectric capacitors in the cell array region, may be formed in the peripheral region. These electrode patterns and pseudo-ferroelectric capacitors may be used as conductive pads for a multilevel conductive interconnection. Since the pseudo-capacitors may be tall, step differences between the cell array region and the peripheral region may be reduced and the aspect ratio of later formed contact openings that reach thereto may be reduced.